VERILOG DESIGN AND TESTBENCH USING EDA PLAYGROUND

EDA Playground is a cloud-based online simulator that enables engineers and students to write, simulate, and debug Verilog designs without installing any software. It provides a user-friendly interface and supports various Verilog simulators like Icarus Verilog (IVL), ModelSim, and Verilator. This guide walks through the process of designing and verifying Verilog code using EDA Playground with Icarus Verilog 12.0 and visualizing waveforms in EPWave.

🔹 Steps to Get Started on EDA Playground

1️⃣ Login and Creating a Project

Open your web browser and go to EDA Playground.
Click on Sign In at the top-right corner (Use Google, GitHub, or create an account).
Once logged in, click on "New" to create a new Verilog project.

🔹 Setting Up the Simulator

2️⃣ Selecting the Icarus Verilog 12.0 Simulator

Under the "Tools & Simulators" tab (left panel), select Icarus Verilog 12.0.
Check the box "Open EPWave after Run" to enable waveform visualization.

🔹 Writing Verilog Code and Testbench

3️⃣ Writing Verilog Design Code

In the "Right Code Window", enter your Verilog module (Design Code).

Example: A simple Full Adder in Verilog.

module full_adder (

input a, b, cin,

output sum, cout );

assign sum = a ^ b ^ cin;

assign cout = (a & b) | (b & cin) | (a & cin);

endmodule

4️⃣ Writing Testbench Code

In the "Left Code Window", write the Verilog testbench.

Example Testbench:

module tb_full_adder;

reg a, b, cin;

wire sum, cout;

// Instantiate Full Adder

full_adder FA (.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));

// Dumpfile for waveform

initial begin

$dumpfile("waveform.vcd");

$dumpvars(0, tb_full_adder);

end

// Test cases

initial begin

$monitor($time, " A=%b B=%b Cin=%b | Sum=%b Cout=%b", a, b, cin, sum, cout);

a = 0; b = 0; cin = 0; #10;

a = 0; b = 1; cin = 0; #10;

a = 1; b = 0; cin = 1; #10;

a = 1; b = 1; cin = 1; #10;

$finish;

end

endmodule

🔹 Compiling and Running the Simulation

5️⃣ Setting Compile Options

In the "Compile Options" field, enter:
-Wall -g2012

- -Wall: Enables all warning messages for better debugging.
- -g2012: Enables SystemVerilog 2012 features.

6️⃣ Running the Simulation

Click "Run" to compile and simulate the design.
If there are no errors, the testbench will execute, and the terminal will display the output.

🔹 Viewing Waveforms in EPWave

7️⃣ Opening the Waveform Viewer

After running the simulation, EPWave will automatically open if the "Open EPWave after Run" checkbox was selected.
You can analyze signals by expanding the hierarchy and dragging signals into the waveform viewer.
Zoom in/out and adjust the time scale to inspect signal transitions.